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1 ? fn6810.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. femtocharge is a trademark of kenet inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. kad5610p dual 10-bit, 250/210/170/125msps a/d converter the kad5610p is a family of low-power, high-performance, dual-channel 10-bit, analog-to-digital converters. designed with intersil?s proprietary femtocharge? technology on a standard cmos process, the family supports sampling rates of up to 250msps. the kad5610p -25 is the fastest member of this pin-compatible family, which also features sample rates of 210msps (kad5610p-21), 170msps (kad5610p-17) and 12 5msps (kad5610p-12). a serial peripheral interface (spi) port allows for extensive configurability, as well as fine control of gain, skew and offset matching between the two converter cores. digital output data is presented in selectable lvds or cmos formats. the kad5610p is available in a 72-contact qfn package with an exposed paddle. performance is specified over the full industrial temper ature range (-40c to +85c). features ? programmable gain, offset and skew control ? 1.3ghz analog input bandwidth ? 60fs clock jitter ? over-range indicator ? selectable clock divider: 1, 2 or 4 ? clock phase selection ? nap and sleep modes ? two?s complement, gray code or binary data format ? ddr lvds-compatible or lvcmos outputs ? programmable built-in test patterns ? single-supply 1.8v operation ? pb-free (rohs compliant) applications ? power amplifier linearization ? radar and satellite antenna array processing ? broadband communications ? high-performance data acquisition ? communications test equipment ? wimax and microwave receivers key specifications ? snr = 60.7dbfs for f in = 105mhz (-1dbfs) ? sfdr = 86.1dbc for f in = 105mhz (-1dbfs) ? power consumption - 411mw @ 250msps - 327mw @ 125msps digital error correction sha 1.25v ainp ainn 10-bit 250msps adc sha binp binn 10-bit 250msps adc vref clkp clkn spi control csb sclk sdio vref ovss avss avdd clkoutp clkoutn d[9:0]p d[9:0]n orp orn outfmt outmode ovdd clkdiv napslp sdo + ? resetn vcm clock generation pin-compatible family model resolution speed (msps) kad5612p-25 12 250 kad5612p-21 12 210 kad5612p-17 12 170 kad5612p-12 12 125 kad5610p-25 10 250 kad5610p-21 10 210 kad5610p-17 10 170 kad5610p-12 10 125 data sheet september 10, 2009
2 fn6810.2 september 10, 2009 ordering information part number (note 1) part marking speed (msps) temp. range (c) package (pb-free) pkg. dwg. # kad5610p-25q72 kad5610p-25 q72ep-i 250 -40 to +85 72 ld qfn l72.10x10d kad5610p-21q72 kad5610p-21 q72ep-i 210 -40 to +85 72 ld qfn l72.10x10d kad5610p-17q72 kad5610p-17 q72ep-i 170 -40 to +85 72 ld qfn l72.10x10d kad5610p-12q72 kad5610p-12 q72ep-i 125 -40 to +85 72 ld qfn l72.10x10d note: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and comp atible with both snpb and pb-free soldering operations. intersi l pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. kad5610p
3 fn6810.2 september 10, 2009 table of contents absolute maximum ratings ......................................... 4 thermal information...................................................... 4 operating conditions.................................................... 4 electrical specifications4 digital specifications .................................................... 6 timing diagrams ........................................................... 7 switching specifications .............................................. 7 pinout/package information......................................... 8 pin descriptions.......................................................... 8 pinout ......................................................................... 10 typical performance curves ........................................ 11 theory of operation ...................................................... 14 functional description ................................................ 14 power-on calibration ................................................. 14 user-initiated reset.................................................... 15 analog input ............................................................... 15 clock input ........... ............... ........... ........... ........... ...... 16 jitter............................................................................ 16 voltage reference...................................................... 17 digital outputs ............................................................ 17 over-range indicator ................................................. 17 power dissipation ...................................................... 17 nap/sleep .................................................................. 17 data format ............................................................... 18 serial peripheral interface ... ........................................ 21 spi physical interface................................................ 21 spi configuration....................................................... 21 device information ................ ..................................... 22 indexed device configuration/ control ........ ............... 22 global device configuration/control.......................... 23 device test ................................................................ 24 spi memory map ....................................................... 25 equivalent circuits ....................................................... 26 adc evaluation platform .......... ............... .............. ...... 27 layout considerations................................................. 27 split ground and power planes................................. 27 clock input considerations ........................................ 27 exposed paddle......................................................... 27 bypass and filtering .................................................. 27 lvds outputs ............................................................ 27 lvcmos outputs ...................................................... 28 unused inputs............................................................ 28 definitions ..................................................................... 28 revision history ........................................................... 29 kad5610p
4 fn6810.2 september 10, 2009 absolute maximum rati ngs thermal information avdd to avss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v ovdd to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v avss to ovss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v analog inputs to avss. . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v clock inputs to avss. . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v logic input to avss . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v logic inputs to ovss. . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical), note 2) ja (c/w) 72 ld qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. electrical specifications all specifications apply under the foll owing conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical sp ecifications at +25c), a in = -1dbfs, f sample = maximum conversion rate (per speed grade). parameter symbol conditions kad5610p-25 (note 3) kad5610p-21 (note 3) kad5610p-17 (note 3) kad5610p-12 (note 3) units min typ max min typ max min typ max min typ max dc specifications analog input full-scale analog input range v fs differential 1.4 1.47 1.54 1.4 1.47 1.54 1.4 1.47 1.54 1.4 1.47 1.54 v p-p input resistance r in differential 1000 1000 1000 1000 input capacitance c in differential 1.8 1.8 1.8 1.8 pf full scale range te m p . d r i ft a vtc full temp 90 90 90 90 ppm/ c input offset voltage v os -10 2 10 -10 2 10 -10 2 10 -10 2 10 mv gain error e g 2 0.6 0.6 0.6 % common-mode output voltage v cm 435 535 635 435 535 635 435 535 635 435 535 635 mv clock inputs inputs common mode voltage 0.9 0.9 0.9 0.9 v clkp,clkn input swing 1.8 1.8 1.8 1.8 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v analog supply current iavdd 170 177 158 165 142 152 128 135 ma 1.8v digital supply current (note 4) i ovdd 3ma lvds 58 65 57 63 55 62 53 60 ma power supply rejection ratio psrr 30mhz, 200mv p-p signal on avdd -36 -36 -36 -36 db kad5610p
5 fn6810.2 september 10, 2009 total power dissipation normal mode pd 3ma lvds 411 438 387 411 357 387 327 351 mw nap mode pd 148 163 142 157 136 151 129 143 mw sleep mode pd csb at logic high 26 2 6 26 26mw nap mode wakeup time (note 5 ) sample clock running 1111s sleep mode wakeup time (note 5) sample clock running 1111ms ac specifications differential nonlinearity dnl -0.5 0.1 2 0.5 -0.5 0.17 0.5 -0.5 0.1 7 0.5 -0.5 0.1 7 0.5 lsb integral nonlinearity inl -0.75 0.2 0.75 -0.75 0.3 0.75 -0.75 0.3 0.75 -0.75 0.3 0.75 lsb minimum conversion rate (note 6) f s min 40 40 40 40 msps maximum conversion rate f s max 250 210 170 125 msps signal-to-noise ratio snr f in = 10mhz 60.8 60.8 61.0 61.0 dbfs f in = 105mhz 59.5 60.7 60.0 60.9 60.2 61.0 60.2 61.0 dbfs f in = 190mhz 60.6 60.8 60.9 60.9 dbfs f in = 364mhz 60.5 60.6 60.7 60.7 dbfs f in = 695mhz 59.9 60.0 60.1 60.0 dbfs f in = 995mhz 59.1 59.2 59.3 59.2 dbfs signal-to-noise and distortion sinad f in = 10mhz 60.7 60.8 60.9 61.0 dbfs f in = 105mhz 59.3 60.7 59.9 60.9 60.0 60.9 60.0 61.0 dbfs f in = 190mhz 60.5 60.8 60.8 60.9 dbfs f in = 364mhz 60.4 60.5 60.6 60.4 dbfs f in = 695mhz 56.5 57.3 56.9 56.6 dbfs f in = 995mhz 49.8 46.9 47.7 49.1 dbfs effective number of bits enob f in = 10mhz 9.8 9.8 9.8 9.8 bits f in = 105mhz 9.5 9.8 9.6 9.8 9.6 9.8 9.6 9.8 bits f in = 190mhz 9.8 9.8 9.8 9.8 bits f in = 364mhz 9.7 9.8 9.8 9.7 bits f in = 695mhz 9.1 9.2 9.2 9.1 bits f in = 995mhz 8.0 7.5 7.6 7.9 bits spurious-free dynamic range sfdr f in = 10mhz 83.0 82.0 78.0 79.0 dbc f in = 105mhz 70.0 86.1 70.0 86.6 70.0 84.6 70.0 85.8 dbc f in = 190mhz 78.0 80.1 81.0 81.2 dbc f in = 364mhz 76.2 77.1 77.9 72.1 dbc f in = 695mhz 60.8 61.9 61.0 61.1 dbc f in = 995mhz 50.2 47.2 47.9 49.4 dbc electrical specifications all specifications apply under the foll owing conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical sp ecifications at +25c), a in = -1dbfs, f sample = maximum conversion rate (per speed grade). (continued) parameter symbol conditions kad5610p-25 (note 3) kad5610p-21 (note 3) kad5610p-17 (note 3) kad5610p-12 (note 3) units min typ max min typ max min typ max min typ max kad5610p
6 fn6810.2 september 10, 2009 intermodulation distortion imd f in = 70mhz -86.1 -92.1 -94.5 -95.1 dbfs f in = 170mhz -96.9 -87.1 -91.6 -85.7 dbfs channel-to- channel isolation f in = 10mhz 90 90 90 90 db f in = 124mhz 90 90 90 90 db word error rate wer 10 -12 10 -12 10 -12 10 -12 full power bandwidth fpbw 1.3 1.3 1.3 1.3 ghz notes: 3. parameters with min and/or max limits are 100% production tested at their worst case temperature extreme (+85c). 4. digital supply current is dependent upon the capa citive loading of the digital outputs. i ovdd specifications apply fo r 10pf load on each digital output. 5. see ?nap/sleep? on page 17 for more detail. 6. the dll range setting must be changed for low speed operation. see table 15 on page 24 for more detail. electrical specifications all specifications apply under the foll owing conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical sp ecifications at +25c), a in = -1dbfs, f sample = maximum conversion rate (per speed grade). (continued) parameter symbol conditions kad5610p-25 (note 3) kad5610p-21 (note 3) kad5610p-17 (note 3) kad5610p-12 (note 3) units min typ max min typ max min typ max min typ max digital specifications parameter symbol conditions min typ max units inputs input current high (sdio,resetn) i ih v in = 1.8v 0 1 10 a input current low (sdio,resetn) i il v in = 0v -25 -12 -5 a input voltage high (sdio, resetn) v ih 1.17 v input voltage low (sdio, resetn) v il .63 v input current high (outmode, napslp, clkdiv, outfmt) (note 7) i ih 15 25 40 a input current low (outmode, napslp, clkdiv, outfmt) i il -40 25 -15 a input capacitance c di 3pf lvds outputs differential output voltage v t 3ma mode 620 mv p-p output offset voltage v os 3ma mode 950 965 980 mv output rise time t r 500 ps output fall time t f 500 ps cmos outputs voltage output high v oh i oh = -500a ovdd - 0.3 ovdd - 0.1 v voltage output low v ol i ol = 1ma 0.1 0.3 v output rise time t r 1.8 ns output fall time t f 1.4 ns kad5610p
7 fn6810.2 september 10, 2009 timing diagrams figure 1. lvds timing diagram (ddr) (see ?digital outputs? on page 17) figure 2. cmos timing diagram (ddr) (see ?digital outputs? on page 17) latency = l cycles t dc t pd t a sample n t cpd inp inn clkn clkp clkoutn clkoutp d[9:0]p d[9:0]n a data n-l + 1 a data n-l b data n-l b data n-l + 1 a data n-l + 2 b data n-l + 2 a data n latency = l cycles t dc t pd t a sample n t cpd inp inn clkn clkp clkout d[9:0] a data n-l + 1 a data n-l b data n-l b data n-l + 1 a data n-l + 2 b data n-l + 2 a data n switching specifications parameter condition symbol min typ max units adc aperture delay t a 375 ps rms aperture jitter j a 60 fs output clock to data propagation delay, lvds mode (note 8) rising edge t dc -260 -50 120 ps falling edge t dc -160 10 230 ps output clock to data propagation delay, cmos mode (note 8) rising edge t dc -220 -10 200 ps falling edge t dc -310 -90 110 ps latency (pipeline delay) l 7.5 cycles overvoltage recovery t ovr 1cycles spi interface (notes 9, 10) sclk period write operation t clk 16 cycles (note 9 read operation t clk 66 cycles sclk duty cycle (t hi /t clk or t lo /t clk) read or write 25 50 75 % sclk duty cycle (t hi /t clk or t lo /t clk ) read or write t s 1cycles csb to sclk setup time read or write t h 3cycles csb after sclk hold time write t ds 1cycles data valid to sclk setup time write t dh 3cycles data valid after sclk hold time read 16.5 cycles data valid after sclk time read 3 cycles kad5610p
8 fn6810.2 september 10, 2009 pinout/package information sleep mode csb to sclk setup time (note 11) read or write in sleep mode t s 150 s notes: 7. the tri-level inputs internal switching thresholds are approx imately .43v and 1.34v. it is adv ised to float the inputs, tie t o ground or avdd depending on desired function. 8. the input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. contact factory for more info if needed. 9. spi interface timing is directly proportional to t s, the adc sample period (4ns at 250msps). 10. the spi may operate asynchronously wi th respect to the adc sample clock. 11. the csb setup time increases in sleep mode due to the reduced powe r state, csb setup time in nap mode is equal to normal mod e csb setup time (4ns min). switching specifications (continued) parameter condition symbol min typ max units pin descriptions pin # lvds [lvcmos] name lvds [lvcmos] function 1, 6, 19, 24, 71 avdd 1.8v analog supply 2-5, 17, 18, 28-35 dnc do not connect 7, 10-12, 72 avss analog ground 8, 9 binp, binn b-channel analog input positive, negative 13, 14 ainn, ainp a-channel analog input negative, positive 15 vcm common mode output 16 clkdiv clock divider control 20, 21 clkp, clkn clock input true, complement 22 outmode output mode (lvds, lvcmos) 23 napslp power control (nap, sleep modes) 25 resetn power on reset (active low, see ?user-initiated reset? on page 15) 26, 45, 55, 65 ovss output ground 27, 36, 56 ovdd 1.8v output supply 37 d0n [nc] lvds bit 0 (lsb) output complement [nc in lvcmos] 38 d0p [d0] lvds bit 0 (lsb) output true [lvcmos bit 0] 39 d1n [nc] lvds bit 1 output complement [nc in lvcmos] 40 d1p [d1] lvds bit 1 output true [lvcmos bit 1] 41 d2n [nc] lvds bit 2 output complement [nc in lvcmos] 42 d2p [d2] lvds bit 2 output true [lvcmos bit 2] 43 d3n [nc] lvds bit 3 output complement [nc in lvcmos] 44 d3p [d3] lvds bit 3 output true [lvcmos bit 3] kad5610p
9 fn6810.2 september 10, 2009 46 rlvds lvds bias resistor (connect to ovss with a 10k , 1% resistor) 47 clkoutn [nc] lvds clock output complement [nc in lvcmos] 48 clkoutp [clkout] lvds clock output true [ lvcmos clkout] 49 d4n [nc] lvds bit 4 output complement [nc in lvcmos] 50 d4p [d4] lvds bit 4 output true [lvcmos bit 4] 51 d5n [nc] lvds bit 5 output complement [nc in lvcmos] 52 d5p [d5] lvds bit 5 output true [lvcmos bit 5] 53 d6n [nc] lvds bit 6 output complement [nc in lvcmos] 54 d6p [d6] lvds bit 6 output true [lvcmos bit 6] 57 d7n [nc] lvds bit 7 output complement [nc in lvcmos] 58 d7p [d7] lvds bit 7 output true [lvcmos bit 7] 59 d8n [nc] lvds bit 8 output complement [nc in lvcmos] 60 d8p [d8] lvds bit 8 output true [lvcmos bit 8] 61 d9n [nc] lvds bit 9 (msb) output complement [nc in lvcmos] 62 d9p [d9] lvds bit 9 (msb) output true [lvcmos bit 9] 63 orn [nc] lvds over range complement, [nc in lvcmos] 64 orp [or] lvds over range true [lvcmos over range] 66 sdo spi serial data output (4.7k pull-up to ovdd is required) 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output 70 outfmt output data format (two?s comp., gray code, offset binary) exposed paddle avss analog ground note: lvcmos output mode functionality is shown in brackets (nc = no connection). pin descriptions (continued) pin # lvds [lvcmos] name lvds [lvcmos] function kad5610p
10 fn6810.2 september 10, 2009 pinout kad5610p (72 ld qfn) top view figure 3. pin configuration avss avdd outfmt sdio 72 71 70 69 68 67 66 65 64 63 62 61 sclk csb sdo ovss orp orn d9p d9n 60 59 d8p d8n d6p d6n d5p d5n d4p d4n clkoutp clkoutn rlvds ovss d3p d3n d2p d2n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avdd dnc dnc dnc dnc avdd avss binp binn avss avss avss ainn ainp 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avdd clkp clkn outmode napslp avdd resetn ovss ovdd dnc dnc dnc dnc dnc 15 16 17 18 vcm clkdiv dnc dnc 33 34 35 36 dnc dnc dnc ovdd d1p d1n d0p d0n 40 39 38 37 58 57 d7p d7n 56 55 ovdd ovss connect thermal pad to avss kad5610p
11 fn6810.2 september 10, 2009 typical performance curves all typical performance charac teristics apply under the follow ing conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = maximum conversion rate (per speed grade). figure 4. snr and sfdr vs f in figure 5. hd2 and hd3 vs f in figure 6. snr and sfdr vs a in figure 7. hd2 and hd3 vs a in figure 8. snr and sfdr vs f sample figure 9. hd2 and hd3 vs f sample 50 55 60 65 70 75 80 85 90 0m 200m 400m 600m 800m 1g input frequency (hz) snr (dbfs) and sfdr (dbc) sfdr @ 125msps sfdr @ 250msps snr @ 125msps snr @ 250msps -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 0m 200m 400m 600m 800m 1g input frequency (hz) hd2 and hd3 magnitude (dbc) hd2 @ 250msps hd2 @ 125msps hd3 @ 125msps hd3 @ 250msps 0 10 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) snr and sfdr snr (dbc) snrfs (dbfs) sfdr (dbc) sfdrfs (dbfs) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) hd2 and hd3 magnitude hd3 (dbc) hd2 (dbfs) hd3 (dbfs) hd2 (dbc) 55 60 65 70 75 80 85 90 40 70 100 130 160 190 220 250 sample rate (msps) snr (dbfs) and sfdr (dbc) sfdr snr -120 -110 -100 -90 -80 -70 -60 40 70 100 130 160 190 220 250 sample rate (msps) hd2 and hd3 magnitude (dbc) hd2 hd3 kad5610p
12 fn6810.2 september 10, 2009 figure 10. power vs f sample in 3ma lvds mode figure 11. differential nonlinearity figure 12. integral nonlinearity figure 13. snr and sfdr vs vcm figure 14. noise histogram figure 15. single-tone spectrum @ 10mhz typical performance curves all typical performance charac teristics apply under the follow ing conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = maximum conversion rate (per speed grade). (continued) 0 50 100 150 200 250 300 350 400 450 40 70 100 130 160 190 220 250 sample rate (msps) total power (mw) -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0 128 256 384 512 640 768 896 1024 code dnl (lsbs) -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0 128 256 384 512 640 768 896 1024 code inl (lsbs) 50 55 60 65 70 75 80 85 90 300 400 500 600 700 800 input common mode (mv) snr (dbfs) and sfdr (dbc) snr sfdr 2050 2051 2052 2053 2054 2055 2056 2057 2058 0 30000 60000 90000 20000 50000 80000 10000 40000 70000 code number of hits 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 frequency (hz) ain = -1.0dbfs snr = 60.7dbfs sfdr = 82.5dbc sinad = 60.7dbfs amplitude (dbfs) kad5610p
13 fn6810.2 september 10, 2009 figure 16. single-tone spectrum @ 105mhz figure 17. single-tone spectrum @ 190mhz figure 18. single-tone spectrum @ 495mhz figure 19. single-tone spectrum @ 995mhz figure 20. two-tone spectrum @ 70mhz figure 21. two-tone spectrum @ 170mhz typical performance curves all typical performance charac teristics apply under the follow ing conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = maximum conversion rate (per speed grade). (continued) 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 frequency (hz) ain = -1.0dbfs snr = 60.7dbfs sfdr = 85.9dbc sinad = 60.7dbfs amplitude (dbfs) 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 amplitude (dbfs) frequency (hz) ain = -1.0dbfs snr = 60.6dbfs sfdr = 78.5dbc sinad = 60.5dbfs 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 ain = -1.0dbfs snr = 60.2dbfs sfdr = 68.9dbc sinad = 59.4dbfs amplitude (dbfs) frequency (hz) 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 ain = -1.0dbfs snr = 58.9dbfs sfdr = 49.8dbc sinad = 49.5dbfs frequency (hz) amplitude (dbfs) 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 imd = -86.1dbfs frequency (hz) amplitude (dbfs) 0m 20m 40m 60m 80m 100m 120m -120 -100 -80 -60 -40 -20 0 imd = -96.9dbfs frequency (hz) amplitude (dbfs) kad5610p
14 fn6810.2 september 10, 2009 theory of operation functional description the kad5610p is based upon a 10-bit, 250msps a/d converter core that utilizes a pipelined successive approximation architecture (figure 22). the input voltage is captured by a sample-hold ampl ifier (sha) and converted to a unit of charge. proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive approximation operations determine the digital code for each input value. the converter pipeline requires six samples to produce a result. digital error correction is also applied, resulting in a total latency of seven and one half clock cycles. this is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. the device contains two a/d converter cores with carefully matched transfer characteristi cs. at start-up, each core performs a self-calibration to minimize gain and offset errors. the reset pin (resetn) is initially set high at power-up and will remain in that state until t he calibration is complete. the clock frequency should remain fixed during this time, and no spi communications should be attempted. recalibration can be initiated via the spi port at any time after the initial self-calibration. power-on calibration the adc performs a self-calibration at start-up. an internal power-on-reset (por) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins (especially 3, 4 and 18) must not be pulled up or down ? sdo (pin 66) must be high ? resetn (pin 25) must begin low ? spi communications must not be attempted a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. the sdo pin requires an external 4.7k pull-up to ovdd. if the sdo pin is pulled low externally during power-up, calibration will not be executed properly. after the power supply has stabilized the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. if a subsequent user-initiated reset is require d, the resetn pin should be connected to an open-drain driver with a drive strength of less than 0.5ma. the calibration sequence is initiated on the rising edge of resetn, as shown in figure 23. the over-range output (or) is set high once resetn is pulled low, and remains in that state until calibration is complete. the or output returns to normal operation at that time , so it is important that the analog input be within the converter?s full-scale range to observe the transition. if the input is in an over-range condition the or pin will stay high, and it will not be possible to detect the end of the calibration cycle. figure 22. adc core block diagram digital error correction sha 1.25v inp inn clock generation 2.5-bit flash 6-stage 1.5-bit/stage 3-stage 1-bit/stage 3-bit flash lvds/lvcmos outputs + ? kad5610p
15 fn6810.2 september 10, 2009 while resetn is low, the output clock (clkoutp/clkoutn) is set low. normal operation of the output clock resumes at the next input clock edge (clkp/clkn) after resetn is deasserted. at 250msps the nominal calibration time is 200ms, while the maximum calibration time is 550ms. user-initiated reset recalibration of the adc can be initiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strengt h of less than 0.5ma is recommended, resetn has an internal high impedance pull-up to ovdd. as is the case during power-on reset, the sdo, resetn and dnc pins must be in the proper state for the calibrat ion to successfully execute. the performance of the kad5610p changes with variations in temperature, supply voltage or sample rate. the extent of these changes may necessitate recalibration, depending on system performance requirements. best performance will be achieved by recalibrating the adc under the environmental conditions at which it will operate. a supply voltage variation of less than 100mv will generally result in an snr change of less than 0.1dbfs and sfdr change of less than 3dbc. in situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. reducing the sample rate by less than 75msps will typically result in an snr change of less than 0.1dbfs and an sfdr change of less than 3dbc. figures 24 and 25 show the effe ct of temperature on snr and sfdr performance with cali bration performed at -40c, +25c, and +85c. each plot shows the variation of snr/sfdr across temperature afte r a single calibration at -40c, +25c and +85c. be st performance is typically achieved by a user-initiated calibration at the operating conditions, as stated earlier. however, it can be seen that performance drift with temperat ure is not a very strong function of the temperature at which the calibration is performed. full-rated performance will be achieved after power-up calibration regardless of the operating conditions. analog input each adc core contains a fully differential input (ainp/ainn, binp/binn) to th e sample and hold amplifier (sha). the ideal full-scale input voltage is 1.45v, centered at the vcm voltage of 0.535v as shown in figure 26. best performance is obtained when the analog inputs are driven differentially. the co mmon-mode output voltage, vcm, should be used to properly bias the inputs as shown in figures 27 through 29. figure 23. calibration timing clkp clkn clkoutp resetn orp calibration begins calibration complete calibration time figure 24. snr performance vs temperature -4 -3 -2 -1 0 1 2 3 -40 -15 10 35 60 85 snr change (dbfs) cal done at +85? temperature (?c cal done at -40? cal done at +25? figure 25. sfdr performance vs temperature -15 -10 -5 0 5 10 15 -40 -15 10 35 60 85 sfdr change (dbc) temperature (?c cal done at -40? cal done at +25? cal done at +85? figure 26. analog input range 1.0 1.8 0.6 0.2 1.4 inp inn vcm 0.535v 0.725v kad5610p
16 fn6810.2 september 10, 2009 an rf transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in figures 27 and 28. this dual transformer scheme is used to improve common- mode rejection, which keeps the common-mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differential input resistance of the kad5610p is 1000 . the sha design uses a switched capacitor input stage (see figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage. this causes a disturbance at the input which must settle before the next sampling point. lower source impedance will result in faster settling and im proved perform ance. therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance. a differential amplifier, as shown in figure 29, can be used in applications that require dc-coupling. in this configuration the amplifier will typically dominate the achievable snr and distortion performance. clock input the clock input circuit is a differential pair (see figure 43). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 impedance ratio will provide increased drive levels. the recommended drive circuit is shown in figure 30. a duty range of 40% to 60% is acceptable. the clock can be driven single-ended, but this will reduce the edge rate and may impact snr performance. the clock inputs are internally self-biased to avdd/2 to facilitate ac coupling. a selectable 2x frequency divider is provided in series with the clock input. the divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate. this allows the use of the phase slip feature, which enables synchronization of multiple adcs. the clock divider can also be controlled through the spi port, which overrides the clkdiv pin setting. details on this are contained in ?serial peripheral interface? on page 21. a delay-locked loop (dll) generates internal clock signals for various stages within the ch arge pipeline. if the frequency of the input clock changes, the dll may take up to 52 s to regain lock at 250msps. t he lock time is inversely proportional to the sample rate. jitter in a sampled data system, clock jitter directly impacts the achievable snr performance. the theoretical relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 31. figure 27. transformer input for general purpose applications adt1-1wt 0.1f kad5610p vcm adt1-1wt 1000pf figure 28. transmission-line transformer input for high if applications adtl1-12 0.1f kad5610p vcm adtl1-12 1000pf 1000pf figure 29. differential amplifier input kad5610p vcm 0.1f 0.22f 69.8o 49.9o 100o 100o 69.8o 348o 348o cm 217o 25o 25o table 1. clkdiv pin settings clkdiv pin divide ratio avss 2 float 1 avdd 4 figure 30. recommended clock drive tc4-1w 200pf 200o 200pf 200pf clkp clkn 1000pf snr 20 log 10 1 2 f in t j ------------------- - ?? ?? = (eq. 1) kad5610p
17 fn6810.2 september 10, 2009 this relationship shows the snr that would be achieved if clock jitter were the only non-ideal factor. in reality, achievable snr is limited by internal factors such as linearity, aperture jitter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in figure 1. the internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. voltage reference a temperature compensated voltage reference provides the reference charges used in the successive approximation operations. the full-scale range of each a/d is proportional to the reference voltage. the nominal value of the voltage reference is 1.25v. digital outputs output data is available as a parallel bus in lvds-compatible or cmos modes. in either case, the data is presented in double data rate (ddr) format with the a and b channel data available on alternating clock edges. when clkout is low channel a data is output, while on the high phase channel b data is presented. figures 1 and 2 show the timing relationships for lvds and cmos modes, respectively. additionally, the drive current for lvds mode can be set to a nominal 3ma or a power-saving 2ma. the lower current setting can be used in designs where the receiver is in close physical proximity to the adc. the applicability of this setting is dependent upon the pcb layout, therefore the user should experiment to determine if performance degradation is observed. the output mode and lvds drive current are selected via the outmode pin as shown in table 2. the output mode can also be controlled through the spi port, which overrides the outmode pin setting. details on this are contained in ?serial peripheral interface? on page 21. an external resistor creates the bias for the lvds drivers. a 10k , 1% resistor must be connected from the rlvds pin to ovss. over-range indicator the over-range (or) bit is asserted when the output code reaches positive full-scale (e.g. 0xfff in offset binary mode). the output code does not wrap around during an over-range condition. the or bi t is updated at the sample rate. power dissipation the power dissipated by the kad5610p is primarily dependent on the sample rate and the output modes: lvds vs cmos and ddr vs sdr. there is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. the output supply dissipation changes to a lesser degree in lvds mode, but is more strongly related to the clock frequency in cmos mode. nap/sleep portions of the device may be shut down to save power during times when operation of the adc is not required. two power saving modes are available: nap, and sleep. nap mode reduces power dissipation to less than 163mw and recovers to normal operation in approximately 1s. sleep mode reduces power dissipation to less than 6mw but requires approximately 1ms to recover from a sleep command. wake-up time from sleep mode is dependent on the state of csb; in a typical application csb would be held high during sleep, requiring a user to wait 150s max after csb is asserted (brought low) prior to writing ?001x? to spi register 25. the device would be fully powered up, in normal mode 1ms after this command is written. wake-up from sleep mode sequence (csb high) ? pull csb low ? wait 150us ? write ?001x? to register 25 ? wait 1ms until adc fully powered on in an application where csb was kept low in sleep mode, the 150s csb setup time is not r equired as the spi registers are powered on when csb is low, the chip power dissipation figure 31. snr vs clock jitter tj = 100ps tj = 10ps tj = 1ps tj = 0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1m 10m 100m 1g snr (db) input frequency (hz) table 2. outmode pin settings outmode pin mode avss lvcmos float lvds, 3ma avdd lvds, 2ma kad5610p
18 fn6810.2 september 10, 2009 increases by ~ 15mw in this case. the 1ms wake-up time after the write of a ?001x? to register 25 still applies. it is generally recommended to keep csb high in sleep mode to avoid any unintentional spi activity on the adc all digital outputs (data, clkout and or) are placed in a high impedance state during nap or sleep. the input clock should remain running and at a fixed frequency during nap or sleep, and csb should be high. recovery time from nap mode will increase if the clock is stopped, since the internal dll can take up to 52s to regain lock at 250msps. by default after the device is powered on, the operational state is controlled by the napslp pin as shown in table 3. the power-down mode can also be controlled through the spi port, which overrides the n apslp pin setting. details on this are contained in ?serial peripheral interface? on page 21. this is an indexed function when controlled from the spi, but a global function when driven from the pin. data format output data can be presented in three formats: two?s complement, gray code and offset binary. the data format is selected via the outfmt pin as shown in table 4. the data format can also be controlled through the spi port, which overrides the outfmt pin setting. details on this are contained in ?serial peripheral interface? on page 21. offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and th e most positive input to 0xfff (all ones). two?s complement coding simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 32 shows this operation. converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 33. mapping of the input voltage to the various data formats is shown in table 5. table 3. napslp pin settings napslp pin mode avss normal float sleep avdd nap table 4. outfmt pin settings outfmt pin mode avss offset binary float two?s complement avdd gray code table 5. input voltage to output code mapping input voltage offset binary two?s complement gray code ?full scale 000 00 000 00 100 00 000 00 000 00 000 00 ?full scale + 1lsb 000 00 000 01 100 00 000 01 000 00 000 01 mid?scale 100 00 000 00 000 00 000 00 110 00 000 00 +full scale ? 1lsb 111 11 111 10 011 11 111 10 100 00 000 01 +full scale 111 11 111 11 011 11 111 11 100 00 000 00 figure 32. binary to gray code conversion 8 9 7 0 1 binary 8 9 7 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 figure 33. gray code to binary conversion 8 9 7 0 1 binary 8 9 7 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? kad5610p
19 fn6810.2 september 10, 2009 figure 34. msb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1d 0 a10 figure 35. lsb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a2 figure 36. ispi write t s t hi t clk t lo r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t h t dhw t dsw spi write csb sclk sdio figure 37. spi read (3 wire mode) (4 wire mode) r/w w1 w0 a12 a11 a10 a9 a2 a1 d7 d6 d3 d2 d1 d7 d3 d2 d1 d0 a0 writing a read command reading data d0 t h t dhr t dvr spi read t hi t clk t lo t dhw t dsw t s csb sclk sdio sdo kad5610p
20 fn6810.2 september 10, 2009 figure 38. 2-byte transfer csb sclk sdio instruction/address data word 1 data word 2 csb stalling figure 39. n-byte transfer csb sclk sdio instruction/address data word 1 data word n last legal csb stalling kad5610p
21 fn6810.2 september 10, 2009 serial peripheral interface a serial peripheral interface (spi) bus is used to facilitate configuration of the device and to optimize performance. the spi bus consists of chip select (csb), serial clock (sclk) serial data input (sdi), and serial data input/output (sdio). the maximum sclk rate is equ al to the adc sample rate (f sample ) divided by 16 for write operations and f sample divided by 66 for reads. at f sample = 250mhz, maximum sclk is 15.63mhz for writing and 3.79mhz for read operations. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust performance or functional parameters. many registers in the available address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined values within defined registers are reserved and s hould not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the serial clock pin (sclk) provides synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin in three-wire mode. the state of the sdio pin is set automatically in the communication protocol (described in the following). a dedicated serial data output pin (sdo) can be activated by setting 0x00[7] high to allow operation in four-wire mode. the spi port operates in a half duplex master/slave configuration, with the kad5610 p functioning as a slave. multiple slave devices can interface to a single master in three-wire mode only, since the sdo output of an unaddressed device is asserted in four wire mode. the chip-select bar (csb) pin determines when a slave device is being addressed. multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). if multiple slave devices are selected for reading at the same time, the results will be indeterminate. the communication protocol begins with an instruction/address phase. the first rising sclk edge following a high to low transition on csb determines the beginning of the two-byte instruction/address command, sclk must be static low before the csb transition. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figures 34 and 35 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode the address is incremented for multi-byte transfers, while in lsb- first mode it?s decremented. in the default mode the msb is r/w, which determines if the data is to be read (active high) or written. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see table 6). the lower 13 bits contain the first address for the data transfer. this relationship is illustrated in figure 36, and timing values are given in ?switching specifications? on page 7. after the instruction/addre ss bytes have been read, the appropriate number of data byte s are written to or read from the adc (based on the r/w bit st atus). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. fo r transfers of four bytes or more, csb is allowed stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point the state machine will reset and terminate the data transfer. figures 37 and 39 illustrate the timing relationships for 2-byte and n-byte transfers, re spectively. the operation for a 3-byte transfer can be inferred from these diagrams. spi configuration address 0x00: chip_port_config bit ordering and spi reset are controlled by this register. bit order can be selected as msb to lsb (msb first) or lsb to msb (lsb first) to accommodate various microcontrollers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to interpret serial data as arriving in lsb to msb order. bit 5 soft reset setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. address 0x02: burst_end if a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. in 3-wire spi mode the burst is ended by pulling the csb pin high. if the device is operated in 2-wire mode the csb pin is not available. in that case, setting the table 6. byte transfer selection [w1:w0] bytes transferred 00 1 01 2 10 3 11 4 or more kad5610p
22 fn6810.2 september 10, 2009 burst_end address determines the end of the transfer. during a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. bits 7:0 burst end address this register value determines the ending address of the burst data. device information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, respectively, can be read from these two registers. indexed device configuration/control address 0x10: device_index_a a common spi map, which can accommodate single- channel or multi-channel devices, is used for all intersil adc products. certain configurat ion commands (identified as indexed in the spi map) can be executed on a per-converter basis. this register determines which converter is being addressed for an indexed command. it is important to note that only a single converter can be addressed at a time. this register defaults to 00h, indicating that no adc is addressed. error code ?ad? is returned if any indexed register is read from without properly setting device_index_a. address 0x20: offset_coarse address 0x21: offset_fine the input offset of each adc core can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 7. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, t he user should first read the register value then write th e incremented or decremented value back to the same register. address 0x22: gain_coarse address 0x23: gain_medium address 0x24: gain_fine gain of the adc core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. ( ?0011? =~ -4.2% and ?1100? =~ +4.2% ) it is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain us ing the registers at 23h and 24h. the default value of each regist er will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write th e incremented or decremented value back to the same register. address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level n apslp pin can select normal operation, nap or sleep modes (refer to ?nap/sleep? on page 17). this functionality can be overridden and controlled through the spi. this is an indexed function when controlled from the spi, but a global function when driven from the pin. this register is not changed by a soft reset. table 7. offset adjustments parameter 0x20[7:0] coarse offset 0x21[7:0] fine offset steps 255 255 ?full scale (0x00) -133lsb (-47mv) -5lsb (-1.75mv) mid?scale (0x80) 0.0lsb (0.0mv) 0.0lsb +full scale (0xff) +133lsb (+47mv) +5lsb (+1.75mv) nominal step size 1.04lsb (0.37mv) 0.04lsb (0.014mv) table 8. coarse gain adjustment 0x22[3:0] nominal coarse gain adjust (%) bit3 +2.8 bit2 +1.4 bit1 -2.8 bit0 -1.4 table 9. medium and fine gain adjustments parameter 0x23[7:0] medium gain 0x24[7:0] fine gain steps 256 256 ?full scale (0x00) -2% -0.20% mid?scale (0x80) 0.00% 0.00% +full scale (0xff) +2% +0.2% nominal step size 0.016% 0.0016% table 10. power-down control value 0x25[2:0] power-down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode kad5610p
23 fn6810.2 september 10, 2009 global device conf iguration/control address 0x70: skew_diff the value in the skew_diff register adjusts the timing skew between the two adcs cores. the nominal range and resolution of this adjustment are given in table 11. the default value of this register after power-up is 00h. address 0x71: phase_slip when using the clock divider, it?s not possible to determine the synchronization of the incoming and divided clock phases. this is particularly important when multiple adcs are used in a time- interleaved system. the phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle when in clk/4 mode, as shown in figure 40. execution of a phase_slip command is accomplished by first writing a ?0? to bit 0 at address 71h followed by writing a ?1? to bit 0 at address 71h (32 sclk cycles). address 0x72: clock_divide the kad5610p has a selectable clock divider that can be set to divide by four, two or one (no division). by default, the tri-level clkdiv pin selects t he divisor (refer to ?clock input? on page 16). this functionality can be overridden and controlled through the spi, as shown in table 12. this register is not changed by a soft reset. address 0x73: output_mode_a the output_mode_a register c ontrols the physical output format of the data, as well as the logical coding. the kad5610p can present output data in two physical formats: lvds or lvcmos. additionally, the drive strength in lvds mode can be set high (3ma) or low (2ma). by default, the tri-level outmode pin selects the mode and drive level (refer to ?digital outputs? on page 17). this functionality can be overridden and controlled through the spi, as shown in table 13. data can be coded in three possible formats: two?s complement, gray code or offset binary. by default, the tri-level outfmt pin selects t he data format (refer to ?data format? on page 18). this functionality can be overridden and controlled through the spi, as shown in table 14. this register is not changed by a soft reset. address 0x74: output_mode_b address 0x75: config_status bit 6 dll range this bit sets the dll operating range to fast (default) or slow. internal clock signals are generated by a delay-locked loop (dll), which has a finite operating range. table 15 shows the allowable sample rate ranges for the slow and fast settings. table 11. differential skew adjustment parameter 0x70[7:0] differential skew steps 256 ?full scale (0x00) -6.5ps mid?scale (0x80) 0.0ps +full scale (0xff) +6.5ps nominal step size 51fs table 12. clock divider selection value 0x72[2:0] clock divider 000 pin control 001 divide by 1 figure 40. phase slip: clk 4 mode, f clock = 1000mhz clk clk ? clk ? slip once clk = clkp ? clkn clk ? slip twice 1.00ns 4.00ns 010 divide by 2 100 divide by 4 table 13. output mode control value 0x93[7:5] output mode 000 pin control 001 lvds 2ma 010 lvds 3ma 100 lvcmos table 14. output format control value 0x93[2:0] output format 000 pin control 001 two?s complement 010 gray code 100 offset binary table 12. clock divider selection (continued) value 0x72[2:0] clock divider kad5610p
24 fn6810.2 september 10, 2009 the output_mode_b and config_s tatus registers are used in conjunction to select the frequency range of the dll clock generator. the method of settin g these options is different from the other registers. the procedure for setting output_mode_b is shown in figure 41. read the contents of output_mode_b and config_status and xor them. th en xor this result with the desired value for output_mode_b and write that xor result to the register. device test the kad5610 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. a static word can be placed on the output bus, or two different words can alternate. in the alternate mode, the values defined as word 1 and word 2 (as shown in table 16) are set on the output bus on alternating cloc k phases. the test mode is enabled asynchronously to t he sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. address 0xc0: test_io bits 7:6 user test mode these bits set the test mode to static (0x00) or alternate (0x01) mode. other values are reserved. the four lsbs in this register (output test mode) determine the test pattern in combination with registers 0xc2 through 0xc5. refer to table ?spi memory map? on page 25. address 0xc2: user_patt1_lsb address 0xc3: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the first user-defined test word. address 0xc4: user_patt2_lsb address 0xc5: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the second user-defined test word. table 15. dll ranges dll range min max unit slow 40 100 msps fast 80 f s max msps figure 41. setting output_mode_b register read config_status 0x75 read output_mode_b 0x74 desired value write to 0x74 table 16. output test modes value 0xc0[3:0] output test mode word 1 word 2 0000 off 0001 midscale 0x8000 n/a 0010 positive full-scale 0xffff n/a 0011 negative full-scale 0x0000 n/a 0100 checkerboard 0xaaaa 0x5555 0101 reserved n/a n/a 0110 reserved n/a n/a 0111 one/zero 0xffff 0x0000 1000 user pattern user_patt1 user_patt2 kad5610p
25 fn6810.2 september 10, 2009 spi memory map table 17. spi memory map addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) indexed/ global spi config 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h g 01 reserved reserved 02 burst_end burst end address [7:0] 00h g 03-07 reserved reserved info 08 chip_id chip id # read only g 09 chip_version chip version # read only g indexed device config/control 10 device_index_a reserved adc01 adc00 00h i 11-1f reserved reserved 20 offset_coarse coarse offset cal. value i 21 offset_fine fine offset cal. value i 22 gain_coarse reserved coarse gain cal. value i 23 gain_medium medium gain cal. value i 24 gain_fine fine gain cal. value i 25 modes reserved power-down mode [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not affected by soft reset i 26-5f reserved reserved 60-6f reserved reserved global deviceconfig/control 70 skew_diff differential skew 80h 71 phase_slip reserved next clock edge 00h g 72 clock_divide clock divide [2:0] 000=pin control 001=divide by 1 010=divide by 2 100=divide by 4 other codes=reserved 00h not affected by soft reset g 73 output_mode_a output mode [2:0] 000 = pin control 001 = lvds 2ma 010 = lvds 3ma 100 = lvcmos other codes = reserved output format [2:0] 000 = pin control 001 = twos complement 010 = gray code 100 = offset binary other codes = reserved 00h not affected by soft reset g 74 output_mode_b dll range 0 = fast 1 = slow 00h not affected by soft reset g 75 config_status xor result read only g 76-bf reserved reserved kad5610p
26 fn6810.2 september 10, 2009 device test c0 test_io user test mode [1:0] 00 = single 01 = alternate 10 = reserved 11 = reserved output test mode [3:0] 00h g 0 = off 1 = midscale short 2 = +fs short 3 = -fs short 4 = checker board 5 = reserved 6 = reserved 7 = one/zero word toggle 8 = user input 9-15 = reserved c1 reserved reserved 00h g c2 user_patt 1_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c3 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c4 user_patt 2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c5 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c6-ff reserved reserved equivalent circuits figure 42. analog inputs figure 43. clock inputs figure 44. tri-level digital inputs figure 45. digital inputs table 17. spi memory map (continued) addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) indexed/ global avdd inp inn avdd f1 f1 f2 f3 f2 f3 csamp 1.6pf csamp 1.6pf to charge pipeline to charge pipeline 1000o avdd clkp clkn avdd avdd to clock- phase generation 11ko 11ko avdd 18ko 18ko avdd input avdd avdd avdd to sense logic 75ko 75ko 75ko 75ko 280o input ovdd ovdd 280 to logic 20k ovdd (20k pull-up on resetn only) kad5610p
27 fn6810.2 september 10, 2009 adc evaluation platform intersil offers an adc evaluation platform which can be used to evaluate any of the kadxxxxx adc family. the platform consists of a fpga based data capture motherboard and a family of adc daughtercards. this usb based platform allows a user to quickly evaluate the adc?s performance at a user?s specific application frequency requirements. more information is available at http://www.intersil.com/co nverters/adc_eval_platform layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer inputs for the analog input and clock signals. locate transformers and terminations as close to the chip as possible. exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for optimal thermal performance. bypass and filtering bulk capacitors should have lo w equivalent series resistance. tantalum is a good choice. for best performance, keep ceramic bypass capacitors very close to device pins. longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. make sure that connections to ground are dire ct and low impedance. avoid forming ground loops. lvds outputs output traces and connections must be designed for 50 (100 differential) characteristic impedance. keep traces direct and minimize bends where possible. avoid crossing ground and power-plane breaks with signal traces. figure 46. lvds outputs figure 47. cmos outputs figure 48. vcm_out output equivalent circuits (continued) d[9:0]p ovdd ovdd 2ma or 3ma 2ma or 3ma data data data data d[9:0]n ovdd d[9:0] ovdd ovdd data vcm avdd 0.535v + ? kad5610p
28 fn6810.2 september 10, 2009 lvcmos outputs output traces and connections must be designed for 50 characteristic impedance. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) which will not be operated do not require connection to ensure optimal adc performance. these inputs can be left floating if they are not used. tri-level inputs (napslp, outmode, outfmt, clkdiv) accept a floating input as a valid state, and ther efore should be biased according to the desired functionality. definitions analog input bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by fft analysis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time required after the rise of the clock in put for the sampling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-d istortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02 gain error is the ratio of the differ ence between the voltages that cause the lowest and highes t code transitions to the full- scale voltage less 2 lsb. it is typically expressed in percent. integral non-linearity (inl) is the maximum deviation of the adc?s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. least significant bit (lsb) is the bit that has the smallest value or weight in a digital word. its value in terms of input voltage is v fs /(2 n -1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the adc out put. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion a nd the appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of the observed magnitude of a spur in the adc fft, caused by an ac signal superimposed on the power supply voltage. signal to noise-an d-distortion (sinad) is the ratio of the rms signal amplitude to the rm s sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one- half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of db when the power of the fundamental is us ed as the reference, or dbfs (db to full-scale) when the conv erter?s full-scale input power is used as the reference. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the largest spurious spectral component. t he largest spurious spectral component may or may not be a harmonic. two-tone sfdr is the ratio of the rms value of the lowest power input tone to the rms value of the peak spurious component, which may or may not be an imd product. kad5610p
29 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6810.2 september 10, 2009 . revision history date revision change 8/6/08 rev 1 initial release of production datasheet 12/5/08 fn6810.0 converted to intersil template. assigned file number fn6810. rev 0 - first release with new file number. applied intersil standards. 1/15/09 fn6810.1 p1; revised key specs p1; changed reset to resetn in block diagram p2; added part marking column to order info p4; moved thermal impedance under thermal info (used to be on p. 7). added theta ja note 2. p4-7; edits throughout the specs table. added notes 8 and 9. revised notes 6 and 7. p7; removed esd section p10-12; revised performance curves throughout p14; user inititated reset section; revised 2nd sentence of 1st paragraph p19; serial peripheral interface; revised 2nd to last sentence of 1st paragraph. spi physical interface; revised 2nd and 3rd sentences of 4th paragraph p20; added last 2 sentences to 1st paragraph of "address 0x24: gain_fine". revised table 8 p21; revised last 2 sentences of "address 0x71: phase_slip". removed figure of "phase slip: clk2 mode, fclock = 500mhz" p24; revised figure 44 p24; table 17; revised bits7:4, addr c0 throughout; formatted graphics to intersil standards 5/14/09 fn6810.2 1)updated pin diagram ; added nap mo de, sleep mode wake up times to spec table 2) added csb,sclk setup time specs for nap,sleep modes to spec table 4) changed spi setup spec wording in spec table 5) change to pin description table for clarification 6) added thermal pad note 7) updated fig 24 and fig 25 and description in text. 8) update multple device usage note on at ?spi physical interface? on page 21 9) added ?reserved? to spi memory map at address 25h 10) added section on ?adc evaluation platform? on page 27 11) intersil standards applied: added pb-free bullet in features and pb-free reflow link in thermal information, added over-temp note reference in spec table. 8/14/09 1. change to spi interface section in spec table, timing in cycles now, added write, read specific timing specs 2. updated spi timing diagrams, figures 36, 37 3. updated wakeup time description in ?nap/sleep? on page 17. 4. removed calibration note in spec table 5) updated user reset section desc. 6) moved label in fig 45 kad5610p
30 fn6810.2 september 10, 2009 kad5610p package outline drawing l72.10x10d 72 lead quad flat no-lead plastic package rev 1, 11/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal ?? 0 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 i dentifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancin g conform to amsey14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view bottom view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 b 6 pin 1 index area 18 1 36 19 0.10 a mc b 4 a 4x 8.50 72x 0.40 72x 0.24 68x 0.50 10.00 10.00 0.90 max 72x 0.24 72x 0.60 68x 0.50 6.00 sq 9.80 sq 6 pin 1 index area exp. dap 6.00 sq. see detail "x" seating plane 0.08 0.10 c c c (4x) 0.15 37 54 72 55

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